PC16552DV

The PC16552DV is an Universal Asynchronous Receiver/Transmitter (UART) features that two serial channels are completely independent except for a common CPU interface and crystal input. On power-up both channels are functionally identical to the 16450. Each channel can operate with on-chip transmitter and receiver FIFOs (FIFO mode) to relieve the CPU of excessive software overhead. In FIFO mode each channel is capable of buffering 16 bytes (plus 3-bits of error data per byte in the RCVR FIFO) of data in both the transmitter and receiver. All the FIFO control logic is on-chip to minimize system overhead and maximize system efficiency. Signalling for DMA transfers is done through two pins per channel (TXRDY# and RXRDY#). The RXRDY# function is multiplexed on one pin with the OUT 2# and BAUDOUT functions. The CPU can select these functions through a new register (Alternate Function Register). Each channel performs serial-to-parallel conversion on data characters.