TSW14J56EVM

The TSW14J56EVM is an Evaluation Module (EVM), next generation of pattern generator and data capture card used to evaluate performances of the new Texas Instruments (TI) JESD204B family of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC). Populated with an Arria V GZ device and using Altera's JESD204B IP solution, the TSW14J56 can be dynamically configurable to support all lanes speeds from 600Mbps to 12.5Gbps, from 1 to 8 lanes, 1 to 16 converters and 1 to 4 octets per frame. Together with the accompanying high speed data converter pro graphic user interface (GUI), it is a complete system that captures and evaluates data samples from ADC EVM's and generates and sends desired test patterns to DAC EVM's.

• Quickly evaluate JESD204B DAC and ADC performance using TI high speed data converter pro software
• Direct connection to all TI JESD204B high speed data converter EVM's using an FMC standard connector
• Quarter rate DDR3 controllers supporting up to 800MHz DDR3 operation
• JESD RX and TX IP cores with 10 routed transceiver channels
• SPI/JTAG reconfigurable JESD core parameters of L, M, K, F, HD, S
• Support for SUBCLASS 0 and 1 operation
• Dynamically reconfigurable transceiver data rate using HSDC Pro software
• An onboard high-speed USB 3.0 to parallel converter bridges the FPGA interface to the host PC&GUI
• 32GB DDR3 SDRAM (split into four independent 512x164GB SDRAMs, total of 2G 16-bit samples)