ISPLSI2032E-110LJ44

The ISPLSI2032E-110LJ44 is a High Density Programmable Logic Device contains 32 registers, 32 universal I/O pins, two dedicated input pins, three dedicated clock input pins, one dedicated global OE input pin and a global routing pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2032E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032E device is the Generic Logic Block (GLB). The GLBs are labelled A0, A1 to A7. There are a total of eight GLBs in the ispLSI 2032E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs.