SN74AUP1G79DCKT

The SN74AUP1G79DCKT is a low-power single positive-edge-triggered D-type Flip-flop fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. When data at the data (D) input meets the setup-time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

• Low noise - Overshoot and undershoot <10% of VCC
• Ioff Supports partial-power-down mode operation
• Input hysteresis allows slow input transition and better switching noise immunity
• Suitable for point-to-point applications
• Latch-up performance exceeds 100mA per JESD 78, Class II
• 3.6V I/O Tolerant to support mixed-mode signal operation
• 5ns at 3.3V Maximum tpd
• 0.9µA Maximum low static-power consumption
• 3pF Typical low dynamic-power consumption
• 1.5pF Typical low input capacitance
• Green product and no Sb/Br