CD74HC4094M96

The CD74HC4094M96 is a 8-stage serial Shift Register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered three-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the OE signal is high. Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge, provides a means for cascading these devices when the clock rise time is slow.

• Buffered inputs
• Separate serial outputs synchronous to both positive and negative clock edges for cascading
• Fanout (over temperature range)
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• Direct LSTTL input logic compatibility
• CMOS Input compatibility
• Green product and no Sb/Br