S25FL512SAGBHIA10

The Cypress S25FL512S device is a flash nonvolatile memory product using: - MirrorBit technology - that stores two data bits in each memory array transistor - Eclipse architecture - that dramatically improves program and erase performance - 65 nm process lithography This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for Double Data Rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock.