ADC3424IRTQ25

The ADC3424IRTQ25 is a quad-channel, 12bit, 125MSPS, analogue-to-digital converter in 56 pin VQFN package. It is a high-linearity, ultra-low power, quad-channel ADC designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signalling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.