MAX6323AUT29+T

The MAX6323AUT29+T is a microprocessor (µP) supervisory circuit with windowed (min/max) watchdog and manual reset in 6 pin SOT-23 package. This supervisory circuit monitors power supplies and µP activity in digital systems. A watchdog timer looks for activity outside an expected window of operation. The complementary RESET is asserted low when VCC falls below the reset threshold or when manual reset input (complementary MR) is asserted low. Complementary RESET remains asserted for at least 100ms after VCC rises above reset threshold and MR (complementary) is deasserted. The watchdog pulse output (complementary WDPO) utilizes an open-drain configuration. It can be triggered either by a fast timeout fault (watchdog input pulses are too close to each other) or a slow timeout fault (no watchdog input pulse is observed within timeout period). The watchdog timeout is measured from last falling edge of watchdog input (WDI) with minimum pulse width of 300ns.