IS42S16400J-7TLI

The IS42S16400J-7TLI is a 64MB Synchronous DRAM is organized as 1,048,576 bits x 16 bits x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 64MB SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216 bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64MB SDRAM includes an AUTO REFRESH MODE and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.