MT46V16M16P-5B IT

The MT46V16M16P-5B IT is a 256MB Double Data Rate (DDR) SDRAM uses double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The DDR SDRAM operates from a differential clock (CK and CK#), the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.