HEF4015BT,652

The HEF4015BT is a 4-bit dual edge-triggered Static Shift Register (serial-to-parallel converter) has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (MR). Information present on D is shifted to the first register position and all the data in the register is shifted one position to the right on the low-to-high transition of CP. A high on MR clears the register and forces Q0 to Q3 to low, independent of CP and D. The clock input's Schmitt trigger action makes the input highly tolerant of slower clock rise and fall times. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.