IS42S32800D-7BLI

The IS42S32800D-7BLI is a Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized in 2Meg x 32-bit x 4 banks. The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3 and 3.3V Vddq memory systems containing 268435456-bit. It is internally configured as a quad-bank DRAM with a synchronous interface. It includes an AUTOREFRESH MODE and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. It has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide pre-charge time and the capability to randomly change column addresses on each clock cycle during burst access.