CD40102BE

The CD40102BE is a 8-stage 2-decade presettable CMOS BCD synchronous Down Counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, it has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. All control inputs and the carry-out/zero-defect output is active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the clock. Counting is inhibited when the carry-in/counter enable (CI/CE\) input is high. The carry-out/zero-defect (CO/ZD\) output goes low when the count reaches zero if the CI/CE\ input is low and remains low for one full clock period.