CD4724BE

The CD4724BE is a 8-bit Addressable Latch with serial-input parallel-output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WD is at a low level. When WD is high, data entry is inhibited, however, all 8 outputs can be continuously read independent of WD and address inputs. A master RESET input is available, which RESETs all bits to a logic "0" level when RESET and WD are at a high level. When RESET is at a high level and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer, the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.