SN74AHCT573DW

The SN74AHCT573DW is an octal Transparent D Latch with 3-state outputs. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered OE input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. OE\ does not affect the internal operations of the latches.