AS7C1024B-12TCN

The AS7C1024B-12TCN is a 5V 128k x 8-bit CMOS Static Random Access Memory (SRAM) organized as 131072 words x 8-bit. It offers 10/12/15/20ns address access time, 5/6/7/8ns output enable access time high speed. It is TTL/LVTTL-compatible, 3-state I/O. Active high and low chip enables permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1024B is guaranteed not to exceed 55mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable and both chip enables. Data on the input pins I/O0 through I/O7 is written on the rising edge of WE or the active-to-inactive edge of CE1 or CE2. To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable or write enable.