CD74HC192E

The CD74HC192E is a 4-bit high-speed CMOS logic presettable synchronous Up/Down Counter. Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a low asynchronous parallel load input (PL). The counter is incremented on the low-to-high transition of the clock-up input (and a high level on the clock-down input) and decremented on the low to high transition of the clock-down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The terminal count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The terminal count down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count.